Designing of integrated circuit (IC) structures on a wafer often relies on photolithography. Photolithographic processes can be used to transfer a pattern of a photomask to a wafer. Feature size, line width, and the separation between features and lines are becoming increasingly smaller.
IC devices are formed in layers with interconnect structures, such as trenches and vias that are used to form interlayer connections between features, such as lines. For example, a via may be used to connect a line feature, such as a gate electrode, in a first layer to a metal line feature in another layer formed above the first layer. The accuracy at which the interconnect structures align with underlying features affects the functionality of the device.